Computer systems typically include a central processing unit (CPU) for performing commands and a main memory for storing data and programs required by the CPU. Thus, increasing the operational speed of the CPU and reducing the access time of the main memory can enhance the performance of the computer system. As will be understood by those skilled in the art, a synchronous DRAM (SDRAM) operates according to control of a system clock and typically provides a short access time when uses as a main memory.
In particular, the operation of the SDRAM is controlled in response to pulse signals generated by transitions of a system clock. Here, the pulse signals are generated during a single data rate SDR mode or a dual data rate DDR mode. The SDR mode generates pulse signals with respect to transitions in one direction (e.g., pulse signals of `high` to `low` or vice versa) to operate a DRAM device. However, the DDR mode generates pulse signals with respect to transitions in both directions (e.g., pulse signals of `high` to `low` and vice versa) to operate the DRAM device.
The DDR mode enables a memory device to have wide bandwidth operation. Thus, the DDR mode is very helpful when making an ultra-high speed SDRAM. However, to implement the DDR mode, the layout area of the memory device typically must be increased because twice as many data lines may need to be provided. Also, in the DDR mode compared with the SDR mode, set-up time and data hold time between data and the clock during reading and writing are reduced, so that auxiliary circuits for delaying an external clock are often necessary. This requirement may lead to further increase in the size of the memory chip. Therefore, only memory devices for ultra-high speed systems typically utilize the DDR mode, whereas other memory devices typically utilize the SDR mode.
Notwithstanding these known aspects of conventional memory devices, there continues to exist a need for improved memory devices and methods of operating same.